1. Field of the Invention
The invention relates to a signal processing arrangement, comprising a comparator circuit, a summing arrangement and a memory connected to the summing arrangement. The comparator has a first signal input for receiving an input signal and a second signal input. The summing arrangement has a third signal input connected to the comparator circuit and a fourth signal input. The memory is connected to the second signal input of the comparator circuit and to the fourth signal input of the summing arrangement.
2. The Prior Art
Such a signal processing arrangement which is, for example, used as a modulator in inter alia imageprocessing apparatus such as TV cameras, is disclosed in an article by H. Bruggeman, "Temporal Filtering Using Pixel Incrementing" published in the Society of Motion Pictures and Television Engineers (SMPTE) Journal, pages 686-694, August 1981.
In that arrangement, a comparator circuit compares the amplitudes of an analog video signal and of a prediction signal, produced by an n bit D/A converter. In doing so the sign of a differential signal which is applied to a summing arrangement is determined. An increment control arrangement and a digital memory containing n bits in each memory location, are further coupled to the summing arrangement. An m bit number stored in the memory is applied to the summing arrangement and added together with the differential signal and an increment signal determined by the increment controller in accordance with a predetermined algorithm, and is returned to the memory. From the n bit number read from the memory n bit m.gtoreq.n are applied to the n-bit D/A converter for forming the prediction signal.
That signal processing arrangement has the disadvantage that when used in image-processing equipment, more specifically if a complete picture must be stored, the memory required therefor is very bulky.